/* SPDX-License-Identifier: GPL-2.0+ */

#ifndef _SDHCI_REG_H
#define _SDHCI_REG_H
#include "cv1835_reg.h"
#define REG_TOP_SD_PWRSW_CTRL (0x1F4)

#define REG_SDIO0_PAD_MASK		(0xFFFFFFF3)
#define REG_SDIO0_PAD_SHIFT		(2)

#define REG_SDIO0_PAD_CLR_MASK (0xC)
#define REG_SDIO0_CD_PAD_REG		(PINMUX_BASE + 0xC04)
#define REG_SDIO0_CD_PAD_VALUE		(1)
#define REG_SDIO0_CD_PAD_RESET		(1)

#define REG_SDIO0_CLK_PAD_REG		(PINMUX_BASE + 0xB04)
#define REG_SDIO0_CLK_PAD_VALUE		(2)
#define REG_SDIO0_CLK_PAD_RESET		(2)

#define REG_SDIO0_CMD_PAD_REG		(PINMUX_BASE + 0xB00)
#define REG_SDIO0_CMD_PAD_VALUE		(1)
#define REG_SDIO0_CMD_PAD_RESET		(2)

#define REG_SDIO0_DAT0_PAD_REG		(PINMUX_BASE + 0xB08)
#define REG_SDIO0_DAT0_PAD_VALUE	(1)
#define REG_SDIO0_DAT0_PAD_RESET	(2)

#define REG_SDIO0_DAT1_PAD_REG		(PINMUX_BASE + 0xB0C)
#define REG_SDIO0_DAT1_PAD_VALUE	(1)
#define REG_SDIO0_DAT1_PAD_RESET	(2)

#define REG_SDIO0_DAT2_PAD_REG		(PINMUX_BASE + 0xB10)
#define REG_SDIO0_DAT2_PAD_VALUE	(1)
#define REG_SDIO0_DAT2_PAD_RESET	(2)

#define REG_SDIO0_DAT3_PAD_REG		(PINMUX_BASE + 0xB14)
#define REG_SDIO0_DAT3_PAD_VALUE	(1)
#define REG_SDIO0_DAT3_PAD_RESET	(2)

#define PAD_SDIO0_CD_REG (PINMUX_BASE + 0x04)
#define PAD_SDIO0_PWR_EN_REG (PINMUX_BASE + 0x14)
#define PAD_SDIO0_CLK_REG (PINMUX_BASE + 0x40)
#define PAD_SDIO0_CMD_REG (PINMUX_BASE + 0x3C)
#define PAD_SDIO0_D0_REG (PINMUX_BASE + 0x44)
#define PAD_SDIO0_D1_REG (PINMUX_BASE + 0x48)
#define PAD_SDIO0_D2_REG (PINMUX_BASE + 0x4C)
#define PAD_SDIO0_D3_REG (PINMUX_BASE + 0x50)

#define REG_SDIO1_PAD_MASK		(0xFFFFFFF3)
#define REG_SDIO1_PAD_SHIFT		(2)

#define REG_SDIO1_PAD_CLR_MASK (0xC)
#define REG_SDIO1_CLK_PAD_REG		(PINMUX_BASE + 0xA14)
#define REG_SDIO1_CLK_PAD_VALUE		(2)

#define REG_SDIO1_CMD_PAD_REG		(PINMUX_BASE + 0xA10)
#define REG_SDIO1_CMD_PAD_VALUE		(1)

#define REG_SDIO1_DAT0_PAD_REG		(PINMUX_BASE + 0xA0C)
#define REG_SDIO1_DAT0_PAD_VALUE	(1)

#define REG_SDIO1_DAT2_PAD_REG		(PINMUX_BASE + 0xA1C)
#define REG_SDIO1_DAT2_PAD_VALUE	(1)

#define REG_SDIO1_DAT1_PAD_REG		(PINMUX_BASE + 0xA20)
#define REG_SDIO1_DAT1_PAD_VALUE	(1)

#define REG_SDIO1_DAT3_PAD_REG		(PINMUX_BASE + 0xA24)
#define REG_SDIO1_DAT3_PAD_VALUE	(1)

#define REG_EMMC_PAD_CLR_MASK (0xC)
#define REG_EMMC_PAD_SHIFT (2)

#define REG_EMMC_RSTN_PAD_REG		(PINMUX_BASE + 0xC24)
#define REG_EMMC_RSTN_PAD_VALUE		(1)

#define REG_EMMC_CLK_PAD_REG		(PINMUX_BASE + 0xC20)
#define REG_EMMC_CLK_PAD_VALUE		(2)

#define REG_EMMC_CMD_PAD_REG		(PINMUX_BASE + 0xC28)
#define REG_EMMC_CMD_PAD_VALUE		(1)

#define REG_EMMC_DAT0_PAD_REG		(PINMUX_BASE + 0xC30)
#define REG_EMMC_DAT0_PAD_VALUE		(1)

#define REG_EMMC_DAT1_PAD_REG		(PINMUX_BASE + 0xC2C)
#define REG_EMMC_DAT1_PAD_VALUE		(1)

#define REG_EMMC_DAT2_PAD_REG		(PINMUX_BASE + 0xC34)
#define REG_EMMC_DAT2_PAD_VALUE		(1)

#define REG_EMMC_DAT3_PAD_REG		(PINMUX_BASE + 0xC38)
#define REG_EMMC_DAT3_PAD_VALUE		(1)

#define SDHCI_RX_DELAY_LINE		(SDHCI_PHY_R_OFFSET + 0x0C)
#define REG_RX_SRC_SEL_MASK		(0xFFCFFFFF) // 0x30c reg_rx_src_sel [21:20]
#define REG_RX_SRC_SEL_CLK_TX_INV		(0) // clk_tx_inv
#define REG_RX_SRC_SEL_PAD_CLK			(1) // pad_clk
#define REG_RX_SRC_SEL_RES			(2) // resvd
#define REG_RX_SRC_SEL_CLK_TX			(3) // clk_tx
#define REG_RX_SRC_SEL_SHIFT		(20) // 0x30c reg_rx_src_sel [21:20]

#define SDHCI_TX_DELAY_LINE		(SDHCI_PHY_R_OFFSET + 0x1C)
#define REG_TX_SRC_SEL_MASK		(0xFFFFF3FF) // 0x31c reg_tx_src_sel [11:10]
#define REG_TX_SRC_SEL_CLK_TX_INV		(0) // clk_tx_inv
#define REG_TX_SRC_SEL_PAD_CLK			(1) // pad_clk
#define REG_TX_SRC_SEL_RES			(2) // resvd
#define REG_TX_SRC_SEL_CLK_TX			(3) // clk_tx
#define REG_TX_SRC_SEL_SHIFT		(10) // 0x31c reg_tx_src_sel [11:10]

#define MMC_MAX_CLOCK		(375000000)
#define MMC_MAX_CLOCK_DIV_VALUE	(0x40009)
#define CLOCK_BYPASS_SELECT_REGISTER	(0x3002030)

#define CVI_SDHCI_VENDOR_OFFSET		0x500
#define CVI_SDHCI_VENDOR_MSHC_CTRL_R	(CVI_SDHCI_VENDOR_OFFSET + 0x8)
#define CVI_SDHCI_VENDOR_EMMC_CTRL_R	(CVI_SDHCI_VENDOR_OFFSET + 0x2C)
#define CVI_SDHCI_VENDOR_A_CTRL_R	(CVI_SDHCI_VENDOR_OFFSET + 0x40)
#define CVI_SDHCI_VENDOR_A_STAT_R	(CVI_SDHCI_VENDOR_OFFSET + 0x44)

#define MAX_TUNING_CMD_RETRY_COUNT 50
#define TUNE_MAX_PHCODE	128
#define TAP_WINDOW_THLD 20
#endif
